A VLSI ARCHITECTURE AND THE FPGA IMPLEMENTATION FOR MULTI-RATE LDPC DECODING

Abstract

<p>Low density parity check (LOPC) codes are utilized frequently in practice as a means of forward error control or error detection. This thesis intends to provide a very large scale integration (VLSI) architecture and corresponding field programmable gate array (FPGA) based implementation for a multi-rate LDPC code.</p> <p><br />Utilizing inherent properties in the quasi-cyclic parity check matrix construction for multiple rates, a nested node situation is exploited. This exploitation produces an architecture that, for this thesis' case study of 802.15-3c, has area savings in the check node update calculation block of roughly half the design that would support multiple rates via parallel instantiation of nodes inside the check node update calculation block.</p>