IMPACT OF SCALING ON NOISE BEHAVIOR OF SUB-100NM MOSFETS

Abstract

<p>This thesis presents the noise characterization, modeling, and simulation of deep sub-100nm bulk MOSFETs and predicts the noise behavior for future technology nodes. There are two main subjects discussed in this thesis. First, we present the impact of scaling of MOSFETs on channel thermal noise. Second, we investigate how the technology development can affect noise performance of a single transistor.</p> <p>In the first topic, analytical MOSFET channel thermal noise expressions are presented and verified. We calibrate our model using experimental data from devices in 60 nm technology node. The technology scaling issue of MOSFETs on noise performance is also examined by applying the parameters predicted in the International Technology Roadmap of Semiconductor (ITRS).</p> <p>In the second topic, a new figure of merit, namely equivalent noise sheet resistance, is defined for the first time to demonstrate the impact of scaling. This new figure of merit represents the intrinsic part of the equivalent noise resistance that excludes the geometry information of the device, which captures the technology related parameters of transistors. By defining equivalent noise sheet resistance, we can provide process information not only for IC designers but also for process engineers.</p>