SAT-Based ATPG for Digital Integrated Circuits Based on Multiple Observations

Abstract

This thesis presents a new approach to improve the efficiency of defect screening during manufacturing test of digital integrated circuits through the use of multiple observations during test generation. To address the limitations of test sets generated based on the single stuck-at fault model, we combine the advantages of multiple-detect and detection at all observable outputs in order to generate test sets that can improve surrogate detection. Imposing additional constraints, such as multiple observations, on the test generation process motivates the development of a new constrained automatic test pattern generation (ATPG) work flow that leverages the recent advancements in the Boolean satisfiability (SAT) problem. Building this ATPG work flow brings its own technical challenges and solutions described in detail in this thesis. To assess the effectiveness of the test sets generated by the proposed ATPG work flow, we evaluate them using coverage metrics for fault models that are not targeted explicitly during test generation.