Advancing Ultra-Wideband Technology: High-Throughput Low-Cost Compact Pulsed Radars for Portable and Mobile Platforms

Abstract

Emerging ultra-wideband (UWB) imaging and sensing applications in the low gigahertz electromagnetic spectrum demand high-throughput, low-cost, and compact radar solutions for portable and mobile sensing. This work introduces a novel UWB pulse radar system capable of capturing thousands of polarimetric radar measurements per second, enabling advanced target detection and identification techniques, including those based on statistical signal processing, machine learning, and artificial intelligence. The realized system achieves a 1:10 fractional bandwidth (FBW) ratio, spanning 500 MHz to beyond 5 GHz at the −10 dB level. The first key contribution is the development of a picosecond pulse generator producing an ultra-stable monocycle-like waveform. This contribution also includes developing a set of rigorous metrics and measurement procedures to evaluate UWB pulse generators, filling a substantial gap in the emerging UWB technology. The second key contribution is the development of a field-programmable gate array (FPGA) controlled dual-channel equivalent-time sampling receiver (ETSR) based on a novel system architecture. The receiver’s unprecedented accuracy and stability is achieved due to the proposed simple but effective calibration method. The method quantifies and corrects the systematic timebase distortion due to the programmable delay chip (PDC). Also, a set of rigorous performance metrics and measurement procedures are proposed to evaluate and compare time-sampling receivers. Similar to the metrics developed for the UWB generators, the receiver metrics have provided the much-needed means of evaluating UWB time-sampling receivers. Finally, a parallelized FPGA architecture is proposed to resolve the main shortcoming of current FPGA-based radars, namely, the low processing throughput. The novel FPGA architecture allows the receiver to achieve a remarkable speed of over 9000 waveforms per second on each channel. As the radar data rate far exceeds the Ethernet link capacity, the FPGA-based processing is leveraged to reduce offloaded data while fully utilizing the radar output with minimal data loss.