Design of a Time-to-Digital Converter and Multi-Time-Gated SPAD Arrays Towards Biomedical Imaging Applications

Abstract

Digital silicon photomultipliers (dSiPMs) and single-photon avalanche diode (SPAD) imagers are optical sensing systems formed from the integration of time-to-digital converters (TDCs) with arrays of highly sensitive photodetectors known as SPADs. TDCs are high-performance mixed-signal circuits capable of timestamping events with picosecond level resolution. The digital operation mechanisms of SPADs allow for their outputs to be sent to TDCs, where the timestamps of individual photon detections are recorded. In recent years, time-resolved SPAD-based sensors have been a heavily studied topic due to their exceptional performance potential in biomedical imaging applications, including time-of-flight (ToF) positron emission tomography (PET), fluorescence lifetime imaging microscopy (FLIM), and diffuse optical tomography (DOT). This work targets the optimization of these sensors in low-cost standard complementary metal-oxide-semiconductor (CMOS) processes. Firstly, this thesis provides a detailed review of the work accomplished in CMOS TDCs and their integration in SPAD-based sensors. Next, a feedback time amplification TDC was designed and tested in the TSMC 65 nm process that can achieve < 5 ps timing resolution in a very compact area of 0.016 mm2. The design is then described for a multi-time-gated array of p+/n-well SPADs that aims to mitigate SPAD dark noise while providing high-speed imaging by applying shifted gate windows simultaneously to an array of SPADs. The p+/n-well SPAD is first characterized in a passive quench configuration where it demonstrated a maximum dark count rate of 44.9 kHz, 18.1% peak PDP at 420 nm, and 0.82 ns timing jitter at a 0.7 V excess bias. While the current multi-time-gated prototype is not fully functional, the measurement results for individual pixels of the multi-time-gated array showed a 3.25 ns median gate window with a 2.2x 10-4 dark count probability for a 0.7 V excess bias, with 440 ps timing resolution and ~1 LSBrms timing jitter. Based on the results, limitations of the current design and sources for future improvement are then discussed in detail.