A CYCLE-ACCURATE SIMULATION INFRASTRUCTURE FOR CACHE-COHERENT INTERCONNECT ARCHITECTURES

Abstract

Maintaining exponential growth in performance of computing systems is no longer derived by the advancement in technological metrics such as clock speed and transistor scaling due to the saturation of Moore's law. Therefore, architectural innovations are a crucial solution in order to maintain this growth. However, these innovations highly demand for comprehensive simulation tools since they provide an infrastructure for evaluating and prototyping new design ideas. Thus, this thesis introduces CacheSim, an efficient, extensible, and cycle-accurate simulator for cache-coherent interconnect architecture. CacheSim enables researchers and computer architects to build reconfigurable simulation infrastructure for multi-core processor chips with a high degree of flexibility of controlling system's configuration parameters such as cache organization, coherence protocol models, and interconnect bus architecture as well as bus arbitration policies. The primary motivation behind developing CacheSim is to use it for architectural explorations, study new design ideas, and evaluate existing ones. Throughout this thesis, we make the following contributions. First, unlike existing state-of-art simulators, we develop a complete cache coherence solution for multi-level cache hierarchy memory systems that support modern interconnecting multi-core bus architectures. Second, CacheSim provides these capabilities to the end-user not only without the need to modify the source code, but also with a high degree of configuribility to control the simulator behaviour through a well-defined input interface. Third, We use this tool to design a novel predictable and coherent bus architecture that provides a considerably tighter latency bound compared to the state-of-art predictable coherent solutions. Finally, we thoroughly validate the simulator features using directed and continuous regression testing plan and code coverage to ensure the functional correctness of the simulator. We release CacheSim as an open-source for the research community to extend and use. We expect CacheSim to significantly accelerate the design and testing of novel research ideas in cache coherency and predictable interconnect architectures used in real-time systems.