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Please use this identifier to cite or link to this item: http://hdl.handle.net/11375/25374
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dc.contributor.advisorDeen, Jamal-
dc.contributor.authorChalich, Yamn-
dc.date.accessioned2020-04-14T06:20:08Z-
dc.date.available2020-04-14T06:20:08Z-
dc.date.issued2020-
dc.identifier.urihttp://hdl.handle.net/11375/25374-
dc.description.abstractSPAD (Single-Photon Avalanche Diode) sensors, capable of detecting down to the single photon level for ultimate sensitivity, have shown great promise as the photodetector of choice for next-generation devices used in positron emission tomography, fluorescence lifetime imaging, light detection and ranging, and more. SPAD fabrication has shifted recently towards custom technologies, 3D stacked designs, and post-processing steps (micro-lenses) to improve performance at the expense of increased cost and complexity. This thesis explores time-gating and multi-junction techniques to improve SPAD performance in standard planar CMOS (Complementary Metal-Oxide-Semiconductor) processes to take advantage of their potential for monolithic integration with other mixed-signal circuitry for simple, low-cost, high-performance imaging solutions. An unbuffered triple-junction SPAD was fabricated to investigate the potential for wavelength distinction, however the top two junctions (n+/p-well and p-well/deep n-well) showed excessive noise, and the deepest junction exhibited a similar spectral response to the top junction, potentially due to a large influence from the process layers over the active area. A time-gated SPAD pixel based on the top junction was also designed and fabricated in the TSMC standard 65 nm CMOS process with a fill-factor of 28.6%. At an excess voltage of 300 mV, it achieved a peak photon detection efficiency of ~3.5% at 440 nm, <1% afterpulsing probability for hold-off times >22ns, and <200 ps timing jitter. Lastly, the potential for high-performance CMOS imaging systems was demonstrated through the development of a prototype open-source, low-cost, highspeed camera built with standard commodity hardware. It achieved 211 frames per second (fps) at its maximum resolution of 1280x1024, and up to 2329 fps at a 256x256 resolution, with a cost well under $1000 USD. It was found to be very competitive to current low-cost, commercial highspeed cameras using a new figure-of-merit comparison and was tested for biological microscopy applications involving C. elegans worms.en_US
dc.language.isoenen_US
dc.titleDesign of Time-Gated CMOS SPADs Towards High-Performance Imagersen_US
dc.title.alternativeDesign of CMOS SPADs Towards High-Performance Imagersen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.description.degreetypeThesisen_US
dc.description.degreeMaster of Applied Science (MASc)en_US
dc.description.layabstractThe CMOS (Complementary Metal-Oxide-Semiconductor) technology process has made accessible the development of highspeed digital circuitry and sophisticated image sensor arrays. SPADs (Single-Photon Avalanche Diodes) capable of detecting single photons for ultimate sensitivity can be fabricated in a standard CMOS process and paves the way for low-cost, next-generation, high-performance, and miniature imaging solutions. In this thesis, a time-gated SPAD implemented in a smaller CMOS technology node not typically investigated in the literature was tested and showed strong overall performance despite suffering from increased noise. A multi-junction SPAD capable of increased photon detecting capabilities was also explored and a time-gated, dual-junction solution was designed and simulated to take advantage of both structures while overcoming the difficulties of integrating them. Finally, a low-cost, highspeed camera is built with standard commodity hardware and a CMOS image sensor to demonstrate the capabilities and ease of developing high-performance imagers comparable to or better than commercial solutions.en_US
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