Towards High Performance and Predictable Adoption of COTS Coherence Protocols for Real-time Systems

Abstract

As modern real-time systems experience increasing demands for performance and data processing, multi-core platforms have become essential. These systems collect vast amounts of data from sensors and cameras, which must be processed by multiple cores via interconnects. Consequently, the traditional task model, where tasks operate independently without sharing data, has evolved toward approaches that support data sharing and inter-core communication. Ensuring performance predictability under these conditions, particularly in meeting strict deadlines, requires hardware architectures designed for accurate worst-case execution time estimates.

To address these challenges, new system architectures need to be explored and evaluated. However, existing cache memory simulators are not suitable for extensibility or for accurately evaluating new designs. This thesis tackles this issue by proposing a cycle-accurate cache system simulator with a flexible and extensible design, allowing computer architects to model complex memory systems with minimal effort. This open-source tool is offering the community a platform for designing cache-related systems. By enabling accurate modeling and exploration of various design alternatives for predictable real-time systems, the simulator allows us to propose new predictable systems. As result, the thesis, firstly, introduces a predictable cache memory system that integrates snooping-based commercial off-the-shelf coherence protocols with legacy real-time arbitration schemes, without requiring architectural changes to the protocol or the arbitration mechanism. This solution is validated through formal timing analysis and evaluated across various cache coherence protocols and arbitration schemes, resulting in 12 different cache-coherent architectures.

Additionally, the thesis presents a scalable and high-performance directory-based solution that supports scalable interconnects and out-of-order processing cores, making it more suitable for systems with a large number of cores compared to snooping-based systems. This approach, independent of specific coherence protocol requirements, ensures predictable performance in multi-core systems by incorporating end-to-end worst-case latency bounds, even when accounting for cache line replacements. The solution's effectiveness is demonstrated through a wide range of experimental configurations, making significant contributions toward the development of predictable, high-performance real-time systems.