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http://hdl.handle.net/11375/28968
Title: | Shared Data Kills Real-Time Cache Analysis. How to Resurrect It? |
Authors: | Bayes, Safin |
Advisor: | Hassan, Mohamed |
Department: | Electrical and Computer Engineering |
Publication Date: | 2023 |
Abstract: | Multi-core embedded systems are highly relevant in modern technology as they meet the growing demands for computational capabilities in various domains, including automotive, IoT, and aerospace, while addressing the constraints of size and power. Embedded systems are indispensable in the real-time domain, where timely and deterministic responses are critical. They provide the essential infrastructure for controlling, monitoring, and ensuring the safety and reliability of critical systems, such as medical devices, industrial automation, and aerospace applications. In the real-time domain, however, multi-core systems complicate timing analysis of real-time tasks due to challenges stemming from contention at shared hardware resources. This thesis identifies and addresses two core problems, which fundamentally invalidate in-isolation cache analysis, forcing techniques to obtain overly pessimistic timing bounds. Problem 1 is a well-known problem which relates to inclusive shared caches, where an interfering core's request may evict a cache line from another core's private cache, leading to unpredictable outcomes. Previous solutions isolate tasks from each other using techniques, such as, cache partitioning or cache locking, to prevent inter-task interference. However, modern applications of real-time systems mandate communication (data-sharing) between tasks. Therefore, recent works enable predictable data-sharing in multi-core systems using cache coherence techniques. This, however, gives rise to Problem 2, a less acknowledged issue, pertaining to coherence interference, where an interfering core may request for a cache line already residing in the private cache of a victim core. Since every access from the victim core may be subjected to such an interfere, existing works assume all requests as cache misses, leading to pessimistic latency bounds. To address these problems, this research proposes a novel methodology utilizing time-based coherence and proves that the in-isolation cache analysis can be restored by integrating timers into the analysis. Results show that the proposed solution reduces the task’s analytical worst-case memory latency (WCML) bound by up-to five times, compared to the State-of-the-Art (SoA) solution. The proposed solution is further extended to Mixed Criticality Systems (MCS), where cores executing tasks of varying criticality levels share resources. Cores with timing requirements operate under time-based coherence, while non-critical cores operate under the conventional performance-oriented coherence protocol. This heterogeneous cache coherence architecture is achieved with minimal overhead and accommodates multiple criticality levels. Furthermore, an adaptive mechanism is proposed to strategically reduce time-based protocol of lower critical cores to the standard coherence protocol, so as to adapt to the changing requirements of higher critical cores. |
URI: | http://hdl.handle.net/11375/28968 |
Appears in Collections: | Open Access Dissertations and Theses |
Files in This Item:
File | Description | Size | Format | |
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Bayes_Safin_202309_MASc.pdf | 3.42 MB | Adobe PDF | View/Open |
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