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http://hdl.handle.net/11375/21983
Title: | On Using Hardware Assertion Checkers for Bit-flip Detection in Post-Silicon Validation |
Authors: | Taatizadeh, Pouya |
Advisor: | Nicolici, Nicola |
Department: | Electrical and Computer Engineering |
Publication Date: | 2017 |
Abstract: | With the rising demand for integrating more features in a single product, modern designs feature more and more functionality on a single die. The complexity resulted from this growth makes it more difficult to guarantee that all errors are detected and fixed before the product is manufactured. Efforts carried out before the design is manufactured, known as pre-silicon verification, are unable to detect all the errors. Electrical errors, such as those caused by cross-talk or power droops, are particularly difficult to catch during the pre-silicon phase because of the insufficient accuracy of device models, which is often traded-off against simulation time. This challenge is further aggravated by the rising number of voltage domains, especially if subtle errors are excited in unique electrical states. These electrically-induced subtle errors most commonly manifest in the logic domain as bit-flips in flip-flops. Therefore, once the design prototypes are available, the verification tasks continue on them to identify and eliminate errors that have escaped pre-silicon verification phase and have the potential to cause catastrophic problems if they remain undetected. This task is commonly referred to as post-silicon validation and has become an important step in the design flow of system-on-chip devices. Limited internal node observability is one of the main challenges of post-silicon validation because it causes long error detection latencies. The existing approaches that try to improve this limited observability usually rely on ad-hoc methods which are difficult to maintain when particular changes are requested from one project to another. Hence in this thesis, we propose novel systematic methods which can be used for automatic generation of on-chip blocks that improve internal observability and reduce error detection latency in post-silicon validation. First we propose an automated methodology that generates and selects hardware assertions for bit-flip detection in post-silicon validation. As part of this methodology, we will introduce two quantitative metrics, the bit-flip coverage estimate and the flip-flop coverage estimate that can be used to assess the quality of the selected assertions. Next, we improve the run-time and the accuracy of our proposed methodology by using emulation platforms that can automatically be integrated into the proposed flow to enable fast, yet accurate assertion selection. Finally in the last contribution, we will propose a novel solution for automatic generation of hardware assertions by leveraging the internal mechanism of Boolean satisfiability solvers, namely learned clauses. In addition, we will formally evaluate the potential of the discovered hardware assertions using an incremental SAT solving approach to assess these hardware assertions for bit-flip detection. We will show that by using this new method, the proportion of errors that can be detected are improved while the area overhead is reduced. State-of-the-art post-silicon validation practices rely primarily on ad-hoc methods for bit-flip detection and there is a lack of systematic methods that can be applied to generic digital blocks. Consequently, the contributions from this thesis are a step towards introducing assertion-based methods and architectures that facilitate systematic bit-flip detection in post-silicon validation. |
URI: | http://hdl.handle.net/11375/21983 |
Appears in Collections: | Open Access Dissertations and Theses |
Files in This Item:
File | Description | Size | Format | |
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Taatizadeh_Pouya_2017April_PhD.pdf | 11.06 MB | Adobe PDF | View/Open |
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