Embedded Deterministic Test for Systems-On-A-Chip

Abstract

<p> Embedded deterministic test (EDT) is a manufacturing test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low cost testers for rapidly achieving high fault coverage, EDT must consciously use the available tester channels to ensure non-disruptive scaling to future devices of increased complexity. The focus of this thesis is to introduce a new EDT approach for systems-on-a-chip (SOCs) that are designed using embedded cores that are intellectual property (IP)-protected.</p> <p> Following an introduction to integrated circuit testing and an overview of the related work, we define the criteria that must be satisfied by the EDT approaches for the future SOCs of ever growing complexity. Then we observe that the necessary amount of compressed volume of test data transferred from the tester to the embedded cores in an SOC varies significantly during the testing process. This motivates a novel approach to compressed SOC testing based on time-multiplexing the tester channels. It is shown how the introduction of test control channels will reduce the number of required test data channels which will then have increased usage, as the embedded cores will receive compressed test data only when necessary. Through the use of modular and scalable hardware for on-chip test control and test data decompression, we define a new algorithmic framework for test data compression that is applicable to SOCs comprising IP-protected blocks. Experimental results indicate that our approach compares to the existing approaches for EDT that have similar design criteria and methodology constraints, while providing a seamless integration to low cost test equipment.</p>