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|Title:||Constrained-Random Stimuli Generation for Post-Silicon Validation|
|Department:||Electrical and Computer Engineering|
|Abstract:||Due to the growing complexity of integrated circuits, significant efforts are undertaken to ensure the design and implementation meet the specification and quality requirements both at the pre-silicon verification stage (before tape-out), as well as at the post-silicon validation stage (on the silicon prototypes). In particular, the constrained-random methods, which subject the design to a large volume of random, yet functionally-compliant stimuli, are widely employed during the pre-silicon stage. Hardware description languages, such as SystemVerilog, have standardized and well-defined features to formalize the constraints including format, sequence control and distribution. Nonetheless, it is not obvious how such features can be efficiently leveraged at the post-silicon stage. In this dissertation, a systematic methodology is proposed to support constrained-random generation and application during post-silicon validation. This includes both software algorithms and on-chip hardware structures. The proposed software translates functional constraints from SystemVerilog into a cube-based representation. A method to design in-field programmable signal generators, which are placed on-chip, can directly expand compacted cubes to extensive random, yet functionally compliant, sequences for post-silicon validation. This approach is extended to also support sequential constraints, as well as the control of the stimuli distribution.|
|Appears in Collections:||Open Access Dissertations and Theses|
Files in This Item:
|Shi_Xiaobing_201604_PhD.pdf||Main dissertation||3.98 MB||Adobe PDF||View/Open|
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