Implementation of Sampled-Data Supervisory Control

Abstract

This thesis focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers, which were introduced by Wang and Leduc. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs.

We first introduce the sampled-data setting from Wang, and then define the sampled-data properties he identified, including the SD controllability property. We then introduce Wang's formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We then discuss Wang's modular and centralized translation method.

We next introduced new modular results for the SD controllability point 3.1, SD controllability point 3.2, SD controllability point 4, activity loop free and S-singular prohibitable behaviour that allow one to verify the properties using only a portion of the system, instead of having to construct the entire system model. This should allow faster verification times as well as allow larger systems to be verified. We then introduce for the first time algorithms to verify Wang's CS Deterministic and non self-loop ALF properties.

The remainder of the thesis focuses on developing algorithms and software to automatically convert a TDES first into an FSM, and then into a VERILOG module. VERILOG is a hardware description language which allows our FSM to be compiled and implemented on digital logic devices such as an FPGA.

We then tested our method by modelling a simple door locking system as TDES, checking that the system satisfies the required sampled-data properties, and then translating the result into VERILOG. The above algorithms and methods have all been implemented as a part of the graphical DES research tool, DESpot.