Skip navigation
  • Home
  • Browse
    • Communities
      & Collections
    • Browse Items by:
    • Publication Date
    • Author
    • Title
    • Subject
    • Department
  • Sign on to:
    • My MacSphere
    • Receive email
      updates
    • Edit Profile


McMaster University Home Page
  1. MacSphere
  2. Open Access Dissertations and Theses Community
  3. Open Access Dissertations and Theses
Please use this identifier to cite or link to this item: http://hdl.handle.net/11375/15283
Full metadata record
DC FieldValueLanguage
dc.contributor.advisorLawford, Marken_US
dc.contributor.advisorNicolici, Nicolaen_US
dc.contributor.advisorDown, Douglasen_US
dc.contributor.authorTaj, Billyen_US
dc.date.accessioned2014-06-18T21:13:30Z-
dc.date.created2013-09-24en_US
dc.date.issued2013-10en_US
dc.identifier.otheropendissertations/8291en_US
dc.identifier.other9399en_US
dc.identifier.other4619848en_US
dc.identifier.urihttp://hdl.handle.net/11375/15283-
dc.description.abstract<p>This thesis proposes a new method to detect routing switch alterations on FPGAs in real-time. By sampling the circuit path at the source and destination, and comparing the samples, it is possible to find out if there has been a routing change in the circuit path. We compare and contrast this probing method with previously established techniques such as Cyclic Redundancy Checks, Built-in-self-tests, Triple Modular Redundancy, Duplication with Comparison, and redesigning the FPGA. The probe method finds the routing error in one clock cycle, using the pre-existing elements on the FPGA, while the FPGA is still operational. This method works on all FPGAs that use the Wilton style switchbox. An automated tool for probing the design circuit is presented in this thesis that applies the probe scheme on a circuit built on the Xilinx Virtex-4 FPGA.</p>en_US
dc.subjectFPGAen_US
dc.subjectSEUen_US
dc.subjectXilinxen_US
dc.subjectroutingen_US
dc.subjectswitchboxen_US
dc.subjecterror detectionen_US
dc.subjectVLSI and circuits, Embedded and Hardware Systemsen_US
dc.subjectVLSI and circuits, Embedded and Hardware Systemsen_US
dc.titleSingle Event Upset error detection on routing tracks of Xilinx FPGAsen_US
dc.typethesisen_US
dc.contributor.departmentComputing and Softwareen_US
dc.date.embargo2014-09-24-
dc.description.degreeMaster of Applied Science (MASc)en_US
dc.date.embargoset2014-09-24en_US
Appears in Collections:Open Access Dissertations and Theses

Files in This Item:
File SizeFormat 
fulltext.pdf
Access is allowed from: 2014-09-23
2.49 MBAdobe PDFView/Open
Show simple item record Statistics


Items in MacSphere are protected by copyright, with all rights reserved, unless otherwise indicated.

Sherman Centre for Digital Scholarship     McMaster University Libraries
©2022 McMaster University, 1280 Main Street West, Hamilton, Ontario L8S 4L8 | 905-525-9140 | Contact Us | Terms of Use & Privacy Policy | Feedback

Report Accessibility Issue