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http://hdl.handle.net/11375/11510
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DC Field | Value | Language |
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dc.contributor.advisor | Nicolici, Nicola | en_US |
dc.contributor.author | Kinsman, Phillip J. | en_US |
dc.date.accessioned | 2014-06-18T16:54:51Z | - |
dc.date.available | 2014-06-18T16:54:51Z | - |
dc.date.created | 2011-10-31 | en_US |
dc.date.issued | 2012-04 | en_US |
dc.identifier.other | opendissertations/6475 | en_US |
dc.identifier.other | 7486 | en_US |
dc.identifier.other | 2321141 | en_US |
dc.identifier.uri | http://hdl.handle.net/11375/11510 | - |
dc.description.abstract | <p>As the number of transistors that are integrated onto a silicon die continues to in- crease, the compute power is becoming a commodity. This has enabled a whole host of new applications that rely on high-throughput computations. Recently, the need for faster and cost-effective applications in form-factor constrained environments has driven an interest in on-chip acceleration of algorithms based on Monte Carlo simula- tions. Though Field Programmable Gate Arrays (FPGAs), with hundreds of on-chip arithmetic units, show significant promise for accelerating these embarrassingly paral- lel simulations, a challenge exists in sharing access to simulation data amongst many concurrent experiments. This thesis presents a compute architecture for accelerating Monte Carlo simulations based on the Network-on-Chip (NoC) paradigm for on-chip communication. We demonstrate through the complete implementation of a Monte Carlo-based image reconstruction algorithm for Single-Photon Emission Computed Tomography (SPECT) imaging that this complex problem can be accelerated by two orders of magnitude on even a modestly-sized FPGA over a 2GHz Intel Core 2 Duo Processor. Futhermore, we have created a framework for further increasing paral- lelism by scaling our architecture across multiple compute devices and by extending our original design to a multi-FPGA system nearly linear increase in acceleration with logic resources was achieved.</p> | en_US |
dc.subject | Monte Carlo | en_US |
dc.subject | Hardware Acceleration | en_US |
dc.subject | Scientific Computing | en_US |
dc.subject | Network on Chip | en_US |
dc.subject | FPGA | en_US |
dc.subject | SPECT | en_US |
dc.subject | Computer and Systems Architecture | en_US |
dc.subject | Computer and Systems Architecture | en_US |
dc.title | A Scalable Framework for Monte Carlo Simulation Using FPGA-based Hardware Accelerators with Application to SPECT Imaging | en_US |
dc.type | thesis | en_US |
dc.contributor.department | Electrical and Computer Engineering | en_US |
dc.description.degree | Master of Applied Science (MASc) | en_US |
Appears in Collections: | Open Access Dissertations and Theses |
Files in This Item:
File | Size | Format | |
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fulltext.pdf | 2.68 MB | Adobe PDF | View/Open |
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