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The MacSphere digital repository system captures, stores, indexes, preserves, and distributes digital research material.Tue, 22 Aug 2017 11:29:21 GMT2017-08-22T11:29:21ZBlind Channel Equalization for SISO and SIMO Channels Using Second Order Statistics
http://hdl.handle.net/11375/21870
Title: Blind Channel Equalization for SISO and SIMO Channels Using Second Order Statistics
Authors: Farid, Ahmed
Abstract: <p> In this thesis we develop several approaches to the problem of blind channel equalization
based on second-order statistics (808). We consider the single-input singleoutput
(8180) system with minimum phase channel where the received signal is
sampled at the symbol rate (T-spaced equalizer). We formulate the equalizer design
criterion as a simple convex optimization problem, where the equalizer can be obtained
efficiently avoiding the local minima problem. </p> <p> We also extend the problem to the single-input multiple-output (8IMO) systems
where the received signal is sampled at an integer multiple of the symbol rate. We
formulate the problem as a convex optimization problem using the features existing
in the channel matrix structure. The problem can be solved efficiently to obtain the
equalizer where a global minima is guaranteed. Moreover, we modify this formulation
and deduce a closed form solution to the equalizer. Although both methods are sensitive
to the channel order as well as existing subspace methods, they perform better
than the subspace methods when the channel matrix is close to being singular.
Furthermore, we propose an efficient direct minimum mean square error (MM8E)
approach to estimate the equalizer. The method does not rely on the channel order
and utilizes the channel matrix structure in SIMO systems. Therefore, it outperforms
existing algorithms including the previously proposed methods. However, due
to the large amount of computations involved in this method we present a new algorithm
that belongs to the same class with moderate computational complexity and
acceptable performance loss with respect to the latter algorithm. </p>Sat, 01 Jan 2005 00:00:00 GMThttp://hdl.handle.net/11375/218702005-01-01T00:00:00ZEmbedded Deterministic Test for Systems-On-A-Chip
http://hdl.handle.net/11375/21869
Title: Embedded Deterministic Test for Systems-On-A-Chip
Authors: Kinsman, Adam
Abstract: <p> Embedded deterministic test (EDT) is a manufacturing test paradigm that combines the compression advantage of built-in self-test with the high fault coverage of deterministic stimuli inherent to methods based on automatic test pattern generation and external testers. Despite enabling the use of low cost testers for rapidly achieving high fault coverage, EDT must consciously use the available tester channels to ensure non-disruptive scaling to future devices of increased complexity. The focus of this thesis is to introduce a new EDT approach for systems-on-a-chip (SOCs) that are designed using embedded cores that are intellectual property (IP)-protected.</p> <p> Following an introduction to integrated circuit testing and an overview of the related work, we define the criteria that must be satisfied by the EDT approaches for the future SOCs of ever growing complexity. Then we observe that the necessary amount of compressed volume of test data transferred from the tester to the embedded cores in an SOC varies significantly during the testing process. This motivates a
novel approach to compressed SOC testing based on time-multiplexing the tester channels. It is shown how the introduction of test control channels will reduce the number of required test data channels which will then have increased usage, as the embedded cores will receive compressed test data only when necessary. Through the use of modular and scalable hardware for on-chip test control and test data decompression, we define a new algorithmic framework for test data compression that is applicable to SOCs comprising IP-protected blocks. Experimental results indicate that our approach compares to the existing approaches for EDT that have similar design criteria and methodology constraints, while providing a seamless integration to low cost test equipment.</p>Wed, 01 Jun 2005 00:00:00 GMThttp://hdl.handle.net/11375/218692005-06-01T00:00:00ZDevelopment of Surface Roughness in AA6111 Aluminum Alloy
http://hdl.handle.net/11375/21868
Title: Development of Surface Roughness in AA6111 Aluminum Alloy
Authors: Oswell, Victoria
Abstract: <p> The effect of strain hardening rate and material strength on the development of surface
roughness in AA6111 was investigated. No measurable change in the rate of roughening,
or in the surface morphology was observed due to altering the strain hardening rate
by using different test temperatures. Changing the material strength and strain hardening
rate by altering the precipitation state also gave no significant change in either roughening
rate or morphology with respect to strain. The development of surface roughness is also
independent of strain history. Samples subjected to an intermediate polish after 20% true
strain resumed roughening at the same rate regardless of amount of previous tensile strain.
The development of surface roughness is dependent on only the strain level to which the
sheet is deformed. The surface morphology seems to be controlled by the combination
and distribution of texture components on the surface. The rate of roughening is grain size
dependent and the surface grain size may provide a key to controlling roughening. </p>Fri, 23 Sep 2005 00:00:00 GMThttp://hdl.handle.net/11375/218682005-09-23T00:00:00ZNon-Linear Time Varying Modeling for Phase Noise in Oscillators Based On a Discrete Recursive Approach
http://hdl.handle.net/11375/21867
Title: Non-Linear Time Varying Modeling for Phase Noise in Oscillators Based On a Discrete Recursive Approach
Authors: Leung, Andrew
Abstract: <p> A unique approach for the modeling of phase noise is examined in this thesis. In
previous work regarding phase noise theory, the memory property of phase is virtually
ignored. The thesis introduces the Discrete Recursive Procedure (DRP): a systematic
approach or methodology to predict phase noise using a discrete recursive algorithm
taking into account the memory property of phase. This discrete recursive algorithm is a
general extension of the Linear Time Varying (LTV) model and is referred to as the NonLinear
Time Varying (NLTV) model. </p> <p> Simulations are performed using the DRP method. Phase fluctuation comparisons
are made between the LTV and the NLTV models for an ideal oscillator. The simulation
results show that the NLTV model taking into account the memory property of phase
makes more realistic phase noise predictions than the LTV model for asymmetrical
Impulse Sensitivity Function (ISF) cases. Phase noise simulation results using the NLTV
model are given for a modified 810-MHz CMOS cross-coupled LC oscillator design. At
90kHz offset, the simulation prediction (-89 dBc/Hz) and the measurement readings (-93
dBc/Hz) are closely matched with a difference of approximately 4 dBc/Hz while the CAD
simulation prediction ( -101. 8) has a difference of 9 dBc/Hz from the measurements. In the
phase noise simulation for the 62-MHz BIT Colpitts oscillator design, the NLTV model
predicts a -26 dBc/decade and -19.5 dBc/decade for the flicker noise and thermal noise
regions in accordance with the theoretical -30 dBc/decade and -20 dBc/decade slopes. </p>Fri, 01 Jul 2005 00:00:00 GMThttp://hdl.handle.net/11375/218672005-07-01T00:00:00Z